1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit memory and more specifically to a 2-Write 3-Read SRAM design using a 12-T storage cell.
2. Description of the Related Art
Integrated circuits frequently employ certain common system building block circuits, such as logic gates and memory blocks to construct the overall system functionality of a given integrated circuit. Each type of system building block circuit is typically optimized to perform a specific function and further optimized for a given criteria, such as operating speed, power consumption, or die area. Furthermore, architecturally distinct designs may be selected to meet a specific design or optimization criteria. For example, a system design may require a static random access memory (SRAM) with two write ports (2-write) and three read ports (3-read).
A conventional SRAM designed to provide two write ports and three read ports typically includes five independent address decoders and extends a conventional six-transistor (6-T) SRAM cell to include fourteen transistors, two write ports and three read ports. Each read port and write port that is added to the 6-T SRAM cell requires a separate word line and two bit lines. The resulting SRAM cell includes fourteen transistors, as well as five horizontal word lines, and ten vertical bit lines. This configuration typically requires more die area for the word lines and bit lines used to connect SRAM cells than the actual transistors used to compose the SRAM cells, resulting in relatively low die area utilization within the SRAM circuit. Low die area utilization within this SRAM circuit (referred to as a 2-write 3-read SRAM) results in increased overall die area. However, minimizing die area is an important requirement because die area directly impacts the cost of manufacturing a given integrated circuit.
One approach to decreasing the die area associated with an SRAM circuit is to use an SRAM circuit with fewer ports and multiplex access to the ports. However, multiplexing access to an SRAM circuit may not meet certain performance requirements and is not a suitable solution in many cases.
As the foregoing illustrates, what is needed in the art is a 2-write 3-read SRAM circuit that is die area efficient and provides high-performance.